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-- Company: 
-- Engineer:
--
-- Create Date:   21:41:25 01/15/2010
-- Design Name:   
-- Module Name:   C:/Custom32Processor/MySOC/Test_Multiplexer.vhd
-- Project Name:  MySOC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Multiplexer
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

-- General package
use work.GeneralProperties.ALL;
 
ENTITY Test_Multiplexer IS
END Test_Multiplexer;
 
ARCHITECTURE behavior OF Test_Multiplexer IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Multiplexer
    PORT(
         InMemory    : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			InExternal : IN  std_logic_vector((bus_size - 1) downto 0);
			InAluOut    : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);	 
         InImediate : IN  std_logic_vector((bus_size - 6) downto 0);
         Sel : IN  MultiplexSignals;
         Y : OUT  std_logic_vector((bus_size - 1) downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal InMemory : std_logic_vector((bus_size - 1) downto 0) := (others => '0');
	signal InExternal : std_logic_vector((bus_size - 1) downto 0) := (others => '0');
   signal InAluOut   : std_logic_vector((bus_size - 1) downto 0) := (others => '0');
	signal InImediate : std_logic_vector((bus_size - 6) downto 0) := (others => '0');
   signal Sel : MultiplexSignals := sel_Imediate;

 	--Outputs
   signal Y : std_logic_vector((bus_size - 1) downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Multiplexer PORT MAP (
          InMemory => InMemory,
			 InExternal => InExternal,
			 InAluOut   => InAluOut,
          InImediate => InImediate,
          Sel => Sel,
          Y => Y
        );    

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
		InMemory <= conv_std_logic_vector(666, bus_size);
		InExternal <= conv_std_logic_vector(1560, bus_size);
		InAluOut <= conv_std_logic_vector(255, bus_size);
		InImediate <= conv_std_logic_vector(480, bus_size - 5);
      wait for 200 ns;

      REPORT "Select external input" SEVERITY WARNING;		
      Sel <= sel_External;
      wait for 200 ns;
		
		REPORT "Select Imediate input" SEVERITY WARNING;		
      Sel <= sel_Imediate;
      wait for 200 ns;
		
		REPORT "Select ALU input" SEVERITY WARNING;		
      Sel <= sel_AluOut;
      wait for 200 ns;
		
		REPORT "Select Memory input" SEVERITY WARNING;		
      Sel <= sel_Memory;
      wait for 200 ns;

      wait;
   end process;

END;
